Analysis of Queueing Displacement Using Switch Port Speedup

Current high-speed packet switching systems, ATM in particular, have large port bu ering requirements. The use of highly integrated ASIC technology for implementing high-degree and high-speed switch fabrics is facing a technology mismatch in the sense that today's chip technology does not allow to integrate on-chip the high-speed switching fabric with the large bu ering requirements. Consequently, many designs are based on the principles of queueing displacement, i.e., they attempt to move the queueing point o -chip. This is usually done by considerably speeding-up the on-chip switch output ports and placing a second external stage of bu ering between the switch fabric and the outgoing link circuitry. Such designs are very popular and are used by many current ATM switch vendors. While such schemes are widely used, no rigorous analysis has so far been o ered to evaluate the design trade-o s and to quantify the design points. The model we use to analyze the performance of the above system is a two-node tandem queueing system. The rst node in the tandem corresponds to the internal bu er while the second node in the tandem corresponds to the external bu er. It is assumed that the internal bu er is capable to transfer c1 cells per time unit to the external bu er, while the external bu er is served at a lower rate of c2 cells per time unit. The work of I. Cidon and M. Sidi was partially supported by Intel, Israel and by the Fund for the Promotion of Research at the Technion. also with SUN Microsystems Labs, 2550 Garcia Avenue, Mountain View, CA 94043, U.S.A. Part of the work of this author was done while visiting SUN Microsystems Labs, Mountain View CA, U.S.A.